Thermal improvement for hotspots on dies in integrated circuit packages

ABSTRACT

Methods and apparatuses for improved integrated circuit (IC) packages are described herein. In an aspect, an IC device package includes an IC die having a contact pad, where the contact pad is located on a hotspot of the IC die. The hotspot is thermally coupled to a thermal interconnect member. In an aspect, the package is encapsulated in a mold compound. In a further aspect, a heat spreader is attached to the mold compound, and is thermally coupled to the thermal interconnect member. In another aspect, a thermal interconnect member thermally is coupled between the heat spreader and the substrate.

This application claims the benefit of U.S. Provisional Appl. No.60/814,876, filed Jun. 20, 2006, which is herein incorporated byreference in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates generally to the field of integrated circuit (IC)device packaging technology, and more particularly to the cooling ofhotspots on IC semiconductor die, heat spreading for IC packages, andthermal interconnection technology in IC packaging.

2. Background Art

Electronic signals are carried by electrical current through conductorsand transistors in a large scale integrated circuit (IC) fabricated onsemiconductor substrate. The energy carried by the electrical current ispartially dissipated along the paths of current flow through the IC inthe form of heat. Heat generation in electronic semiconductor ICs isalso known as power consumption, power dissipation, or heat dissipation.The heat generated, P, in an IC is the sum of dynamic power, P_(D), andstatic power, P_(S):

P=P _(D) +P _(S) =ACV ² f+VI _(leak)

where A is the gate activity factor, C is the total capacitance load ofall gates, V is the peak-to-peak supply voltage swing, f is thefrequency, and I_(leak) is the leakage current. The static power term,P_(S)=VI_(leak), is the static power dissipated due to leakage current,I_(leak). A further description regarding static power is provided inKim et al, Leakage Current: Moore's Law Meets Static Power, IEEEComputer, 36(12): 68-75, Dec. 2003, which is incorporated by referenceherein in its entirety.

The dynamic power term, P_(D)=ACV²f, is the dynamic power dissipatedfrom charging and discharging the IC device capacitive loads. Dynamicpower consumption is thus proportional to the operating frequency andthe square of operating voltage. Static power consumption isproportional to the operating voltage. Advances in transistor gate sizereduction in semiconductor IC technology have reduced the operatingvoltage and power dissipation for single transistors. However, on-chippower densities are expected continue to rise in future technologies asthe industry continues to follow the trend set forth by Moore's Law. In1965, Intel co-founder Gordon Moore predicted that the number oftransistors on a chip doubles about every two years. In addition to theincreased number of transistors on a chip, the operating frequenciesalso double about every two years according to the 2004 InternationalTechnology Roadmap for Semiconductors (ITRS Roadmap)(http://www.itrs.net/Common/2004Update/2004_(—)00_Overview.pdf). Becauseof the increased difficulties in controlling noise margins as voltagedecreases, operating voltages can no longer be reduced as quickly as inthe past for 130 nm gate lengths and smaller. Consequently, on-chippower dissipation will continue to rise. See Table 6 of the ITRSRoadmap. With the increased use of 65 nm technology in foundry processesand the commercialization of 45 nm technology, power consumption is nowa major technical problem facing the semiconductor industry.

Another characteristic of IC chips is the uneven distribution oftemperature on a semiconductor die. More and more functional blocks areintegrated in a single chip in system-on-chip (SOC) designs. Higherpower density blocks create an uneven temperature distribution and leadto “hotspots,” also known as “hot blocks,” on the chip. Hotspots canlead to a temperature difference of about 5° C. to roughly 30° C. acrossa chip. Further description of hotspots is provided in Shakouri andZhang, “On-Chip Solid-State Cooling For Integrated Circuits UsingThin-Film Microrefrigerators,” IEEE Transactions on Components andPackaging Technologies, Vol. 28, No. 1, March, 2005, pp. 65-69, which isincorporated by reference herein in its entirety.

Since carrier mobility is inversely proportional to temperature, theclock speed typically must be designed for the hottest spot on the chip.Consequently, thermal design is driven by the temperature of theseon-chip hotspots. Also, if uniform carrier mobility is not achievedacross the IC die due to on-chip temperature variations across the die,this may result in variations in signal speed and in complicatingcircuit timing control.

Heat spreaders, including drop-in heat spreaders, heat sinks, and heatpipes have been used in the past to enhance thermal performances of ICpackages. Further descriptions of example heat spreaders are provided inU.S. Pat. No. 6,552,428, entitled “Semiconductor Package Having AnExposed Heat Spreader”, issued Apr. 22, 2003, which is incorporated byreference herein in its entirety. Further descriptions of example heatpipes are provided in Zhao and Avedisian, “Enhancing Forced AirConvection Heat Transfer From An Array Of Parallel Plate Fins Using AHeat Pipe, Int. J. Heat Mass Transfer, Vol. 40, No. 13, pp. 3135-3147(1997).

For example, FIG. 1A shows a die up plastic ball grid array (PBGA)package 100 integrated with a drop-in heat spreader 104. In package 100,IC die 102 is attached to a substrate 110 by die attach material 106 andis interconnected with wirebond 114. Package 100 can be connected to aprinted wire board (PWB) (not shown) by solder balls 108. A drop-in heatspreader 104 is mounted to substrate 110, and conducts heat away fromdie 102. Mold compound 112 encapsulates package 100, including die 102,wirebond 114, all or part of drop-in heat spreader 104, and all or partof the upper surface of substrate 110. Drop-in heat spreader 104 iscommonly made of copper or other material that is thermally moreconductive than mold compound 112. Thermal conductivity values arearound 390 W/m*° C. for copper and 0.8 W/m*° C. for mold compoundmaterials, respectively.

Thermal enhancement methods, such as shown in FIG. 1A, rely on heatremoval from the entire chip or from the entire package. They maintainsemiconductor temperature below the limit of operation threshold bycooling the entire chip indiscriminately. These methods are oftenineffective and inadequate to reduce the temperature of the hotspotsrelative to the rest of the chip, such that operation of the chip isstill limited by the hotspots.

For example, FIG. 1B shows a perspective view of a silicon die 102, andin particular shows the temperature distribution on silicon die 102 in aPBGA with no external heat sink. The temperature difference across thedie 102 is 13.5° C. FIG. 1C shows die 102 of FIG. 1B, illustrating theeffect of adding a drop in heat spreader and a heat sink to the packageof die 102. The temperature difference remains 13.0° C. with a largesize (45 mm×45 mm×25 mm) external aluminum pin-fin heat sink attached ontop of the exposed drop-in heat spreader. Both the drop-in heat spreaderand the external heat sink are ineffective to reduce the on-chiptemperature differences caused by the hot spots.

Active on-chip cooling methods that use electrical energy to remove heatfrom the IC chip are known in the art. For example, some have suggestedpumping liquid coolant through micro-channels engraved in silicon tocirculate on the semiconductor die and carry away waste heat. A furtherdescription regarding liquid cooling is provided in Bush, “Fluid CoolingPlugs Direct onto CMOS,” Electronic News, Jul. 20, 2005,http://www.reed-electronics.com/electronicnews/article/CA626959?nid=2019&rid=550846255),which is incorporated by reference herein in its entirety. See alsoSinger, “Chip Heat Removal with Microfluidic Backside Cooling,”Electronic News, Jul. 20, 2005, which is incorporated by referenceherein in its entirety.

Other active cooling methods have been developed in an attempt toprovide active on-chip cooling using a thin-film thermoelectric cooler(TEC). A further description regarding on-chip cooling with TECs isprovided in Snyder et al, “Hot Spot Cooling using EmbeddedThermoelectric Coolers,” 22nd IEEE SEMI-THERM, Symposium, pp. 135-143(2006), which is incorporated by reference herein in its entirety.

These active cooling methods require exotic and expensive fluidcirculation or micro-refrigeration systems and add to the total powerconsumption of the package that must be removed. A separate power supplymust also be integrated into the IC package to drive the fluid pumpingor the TEC systems. These can be costly and can decrease componentreliability. Because these solutions are typically expensive, their useis limited in cost sensitive applications such as consumer electronicdevices.

These cooling methods as discussed above are inadequate and/or difficultand expensive to implement for commercial applications. What is neededis an inexpensive and reliable system and method of selective heatremoval from hot blocks or hotspots on semiconductor dice.

BRIEF SUMMARY OF THE INVENTION

Methods and apparatuses for improved integrated circuit (IC) packagesare described herein.

In an aspect of the invention, an IC device package includes an IC diehaving a contact pad, where the contact pad is located on a hotspot on asurface of the IC die. A thermal interconnect member is attached to thehot spot. In an aspect of the invention, the package is encapsulated ina mold compound. In a further aspect of the invention, the die andthermal interconnect member are also electrically coupled.

In an aspect of the invention, the package also includes a heatspreader. The heat spreader may be thermally coupled to the thermalinterconnect member. In a further aspect, the heat spreader is alsoelectrically coupled to the thermal interconnect member. In an aspect ofthe invention, the heat spreader is completely encapsulated in moldcompound. In another aspect, the heat spreader is at least partiallyexposed. In an aspect of the invention, the heat spreader has a platedarea at a location corresponding to a location of the thermalinterconnect member.

In an aspect of the invention, an integrated circuit (IC) package ismanufactured by a method which includes attaching an IC die to asubstrate, enabling electrical interconnection between the die and thesubstrate through a wire bonding process, coupling at least one thermalinterconnect member to at least one contact pad on the die, andencapsulating the package in a mold compound or other encapsulatingmaterial. In another aspect of the invention, a portion of a thermalinterconnect member (or a plurality of thermal interconnect members) isexposed. In an example aspect, an entire layer of mold compound isremoved to expose the thermal interconnect member. In another exampleaspect, a cavity is carved into the mold compound to expose the thermalinterconnect member.

In an aspect of the invention, the manufacturing method further includescoupling a heat spreader to the exposed thermal interconnect member. Inan aspect, the heat spreader has plating at one or more locationcorresponding to the thermal interconnect member.

In another aspect of the invention, a die is analyzed to determine alocation of at least one hotspot on a surface of the die that resultsfrom operation of the die. In an aspect, the analysis includes mappingfunctional blocks of the die to determine one or more hotspots. Inanother aspect, the analysis includes performing a thermal analysis ofthe die during operation to locate one or more hotspots.

In another aspect of the invention, a package includes a substratehaving opposing first and second surfaces, an IC die mounted to thefirst surface of the substrate, a heat spreader, and a thermalinterconnect member that couples the first surface of the substrate to asurface of the heat spreader.

These and other objects, advantages and features will become readilyapparent in view of the following detailed description of the invention.Note that the Summary and Abstract sections may set forth one or more,but not all exemplary embodiments of the present invention ascontemplated by the inventor(s).

BRIEF DESCRIPTION OF THE DRAWINGS/FIGURES

The accompanying drawings, which are incorporated herein and form a partof the specification, illustrate the present invention and, togetherwith the description, further serve to explain the principles of theinvention and to enable a person skilled in the pertinent art to makeand use the invention.

FIG. 1A illustrates a conventional IC package.

FIGS. 1B and 1C illustrate temperature distributions across a die in theconventional IC package of FIG. IC using conventional cooling methods.

FIGS. 2A-2B illustrate perspective views of example ball grid array(BGA) packages with cut away portions, according to exemplaryembodiments of the invention.

FIG. 2C illustrates a cross-sectional view of an example BGA package,according to an exemplary embodiment of the invention.

FIG. 2D illustrates a perspective view of an example ball grid array(BGA) package with a cut away portion, according to an exemplaryembodiment of the invention.

FIG. 2E illustrates a perspective view of an example ball grid array(BGA) package with a cut away portion, according to an exemplaryembodiment of the invention.

FIG. 2F illustrates a cross-sectional view of an example BGA package,according to an exemplary embodiment of the invention.

FIGS. 3A-3E illustrate cross-sectional views of example fine pitch ballgrid array (BGA) packages having a heat spreader, according to exemplaryembodiments of the invention.

FIGS. 4A-4B illustrate cross-sectional views of example plastic ballgrid array (PBGA) packages having a heat spreader, according toexemplary embodiments of the invention.

FIGS. 5A-5C illustrate cross-sectional views of example leadframepackages having a heat spreader, according to exemplary embodiments ofthe invention.

FIGS. 6A-6B illustrate example no-lead quad flat package (QFN) packageshaving a heat spreader, according to exemplary embodiments of theinvention.

FIG. 7A shows a flowchart providing examples steps for assembling anintegrated circuit package, according to exemplary embodiments of theinvention.

FIG. 7B-7F illustrate cross-sectional views of an integrated circuitpackage during various phase of assembly, where encapsulation occursbefore heat spreader attachment, according to exemplary embodiments ofthe invention.

FIG. 8A shows a flowchart providing examples steps for assembling anintegrated circuit package, according to exemplary embodiments of theinvention.

FIG. 8B-8C illustrate cross-sectional views of attaching a heat spreaderto an integrated circuit package, according to exemplary embodiments ofthe invention.

FIG. 9A shows a flowchart providing examples steps for assembling anintegrated circuit package, according to exemplary embodiments of theinvention.

FIG. 9B-9D illustrate cross-sectional views of an integrated circuitpackage during various phase of assembly, where encapsulation occursafter heat spreader attachment, according to exemplary embodiments ofthe invention.

FIG. 9E shows a flowchart providing examples steps for assembling anintegrated circuit package, according to exemplary embodiments of theinvention.

FIG. 9F-9H illustrate cross-sectional views of an integrated circuitpackage during various phase of assembly, where encapsulation occursafter heat spreader attachment, according to exemplary embodiments ofthe invention.

FIGS. 10A-10C illustrate cross-sectional views of example BGA packageshaving a heat spreader thermally coupled to the package substrate,according to exemplary embodiments of the invention.

Embodiments of the present invention will now be described withreference to the accompanying drawings. In the drawings, like referencenumbers indicate identical or functionally similar elements.Additionally, the left-most digit(s) of a reference number identifiesthe drawing in which the reference number first appears.

DETAILED DESCRIPTION OF THE INVENTION Introduction

Methods, systems, and apparatuses for IC device packaging technology aredescribed herein. In particular, methods, systems, and apparatuses forthe (1) cooling of hotspots on IC semiconductor die, (2) heat spreadingfor IC packages, and (3) thermal interconnection technology in ICpackaging are described.

References in the specification to “one embodiment,” “an embodiment,”“an example embodiment,” etc., indicate that the embodiment describedmay include a particular feature, structure, or characteristic, butevery embodiment may not necessarily include the particular feature,structure, or characteristic. Moreover, such phrases are not necessarilyreferring to the same embodiment. Further, when a particular feature,structure, or characteristic is described in connection with anembodiment, it is submitted that it is within the knowledge of oneskilled in the art to effect such feature, structure, or characteristicin connection with other embodiments whether or not explicitlydescribed.

The present specification discloses one or more embodiments thatincorporate the features of the invention. The disclosed embodiment(s)merely exemplify the invention. The scope of the invention is notlimited to the disclosed embodiment(s). The invention is defined by theclaims appended hereto.

Furthermore, it should be understood that spatial descriptions (e.g.,“above”, “below”, “left,” “right,” “up”, “down”, “top”, “bottom”, etc.)used herein are for purposes of illustration only, and that practicalimplementations of the structures described herein can be spatiallyarranged in any orientation or manner.

Embodiments of the invention provide enhanced heat removal at desiredlocations on the surface of the semiconductor die. In conventionaldevices, entire IC die and/or IC package surfaces are cooled to keep thepeak temperatures on the IC die below an operation threshold limit. Incontrast, in an embodiment, one or more thermal interconnect members arecoupled to one or more surfaces of an IC die. The thermal interconnectmembers remove heat from hot spots on the die. The thermal interconnectmembers provide one or more paths for heat transfer from the IC diethrough a mold that encapsulates the die to the outside environment.

In a further embodiment, the thermal interconnect members are coupled toa heat spreader. When the thermal interconnect members are coupled to aheat spreader integrated in the package, the thermal interconnectmembers function as thermal bridges through the mold that fills a gapbetween the die and heat spreader. Locations for the positioning thethermal interconnect members in contact with the die may be selected, byusing an on-chip power density map and/or based on chip layout, forexample.

In embodiments, one or more of the thermal interconnect members may beimplemented with or without a heat spreader in all types of IC packagessuch as plastic ball grid array (PBGA), fine pitch ball grid array(BGA), land grid array (LGA), pin grid array (PGA), post-molded plasticleadframe packages such as quad flatpack (QFP) and no-lead quad flatpack(QFN) packages, and micro leadframe packages (MLP). For example,embodiments may be implemented in all wire-bond packages encapsulatedwith molded plastic to provide on-chip hot spot cooling as well asimproving device overall heat dissipation capability.

Example Embodiments of Thermal Interconnect Members

In embodiments, thermal interconnect members are thermally conductivesolder balls, solder bumps, posts, or other thermally conductivestructures. In further embodiments, the thermal interconnect members arealso electrically conductive. For the purposes of illustration,exemplary embodiments using a solder ball-based thermal interconnectstructure are referred to below to explain the principles of theinvention. However, embodiments may use other thermal interconnectstructures. Thermal interconnect members may be made of a metal, such asgold, copper, aluminum, silver, nickel, or tin, may be made of acombination of metals/alloy, such as solder, a eutectic (tin, lead), alead-free solder, may be made of a thermally conductive epoxy or otheradhesive material, or may be made of other thermally conductivematerials. In an embodiment, a thermal interconnect member is made of acore material that is coated with a bonding material such as solder,gold, silver, an epoxy, or other joining materials that mechanicallybonds the thermal interconnect member with contact pads on asemiconductor die. In an embodiment, thermal interconnect members may bepre-deposited at pre-defined contact pads on a surface of thesemiconductor die. In a further embodiment, one or more thermalinterconnect members are also coupled to a heat spreader.

By attaching thermal interconnect members with a high power dissipationdensity to contact pads at areas on the die, which may be referred to aspoints or “blocks”, heat generated within these hotspots (also known ashot blocks) can be conducted away from the IC die directly to theexternal environment or through a thermally conductive heat spreader (ifpresent) to the environment. In an embodiment, the placement of the oneor more thermal interconnect members is based on a power map of asemiconductor die for a specific application. In another application,the same semiconductor die may have different on-chip thermalinterconnect member locations if a different power maps results from theapplication. For example, this may occur when different functionalblocks of the die switch from a “power-up” mode to a “power-down” mode,or vice versa, for different applications.

In an embodiment, a die is analyzed to determine a location of at leastone hotspot on a surface of the die that results from operation of thedie. In one embodiment, the analysis includes mapping functional blocksof the die to determine one or more hotspots. In another embodiment, theanalysis includes performing a thermal analysis/measurement (e.g., asshown in FIGS. 1B and 1C) of the die during operation to locate one ormore hotspots. As a result of analysis, one or more hotspots may bedetermined that are located on a surface of the die among otherlocations of the die that are relatively less hot (cooler) than thehotspots, and thus may need relatively less heat spreading than thehotspots. Thus, according to embodiments of the present invention, theone or more determined hotspots have corresponding thermal interconnectmembers specifically targeted to them (mechanically/thermally coupled tothem), to conduct heat from the hotspots, while conducting less heatfrom the cooler spots/areas (because a thermal interconnect has not beendirectly applied to the cooler spots/areas). In this manner, a thermalsignature of the die surface can be made more uniform (cooling thehotspots to be closer in temperature to the cooler spots/areas).

For example, some dies have peripheral bond pads (e.g., formed in one ormore rings) at a surface of the die for internal I/O signals to beaccessible externally from the die. First ends of wire bonds attach tothe peripheral bond pads, and second ends of the wire bonds attach tothe package substrate or other structures of the package. Inembodiments, contact pads are attached to hotspots located in a centralregion of the surface of the die outside of the peripheral region of thewire bond pads, but in embodiments one or more contact pads may belocated in a peripheral region of the surface of the die.

FIGS. 2A-2B show perspective cut-away views of an exemplary embodimentof a die up BGA package 200. FIG. 2C illustrates a side cross sectionalview of package 200. In package 200, an IC die 102 is electricallyconnected by a plurality of wire bonds 114 to conductive features (e.g.,traces, bond fingers, etc) such as a trace 210 on a top surface of asubstrate 110. The conductive features on the top surface of substrate110 are electrically coupled through substrate 110 (e.g., through one ormore electrically and/or non-electrically conductive layers) to solderball pads on a bottom surface of substrate 110. Solder balls 108 arecoupled to the solder ball pads, and are configured to be coupled to acircuit board, such as a printed circuit board (PCB) or printed wireboard (not shown in FIGS. 2A-2C).

As shown in FIG. 2A, a top surface of die 102 has at least one contactpad 202, to which at least one thermal interconnect member 208 iscoupled. In embodiments, die 102 can have any number of contact pads202, each for coupling with a thermal interconnect member 208. Contactpads 202 are located at pre-determined hotspots (not shown) on die 102.Hotspots of die 102 are locations on die 102 that are generally hotterthan other locations on die 102, although contact pads 202 may belocated on locations of die 102 that are not necessarily hotter thanother locations of die 102. Mold compound 112 encapsulates package 200.In the embodiments of FIGS. 2B-2C, thermal interconnect members 208 arecompletely covered with mold compound 112.

FIGS. 2D-2E show perspective views of an exemplary embodiment of a dieup BGA IC package 250. FIG. 2F illustrates a side cross sectional viewof package 250. Package 250 is similar to package 200, except that moldcompound 112 does not encapsulate top surfaces 252 of thermalinterconnect members 208. In an embodiment, a top layer of mold compound112 is removed to expose surfaces 252 of thermal interconnect members208. In such an embodiment, thermal interconnect members 208 aretruncated to form the planar exposed surfaces 252 of thermalinterconnect members 208, and surfaces 252 are co-planar with a topsurface of mold compound 112. Surfaces 252 can also be referred to asthermal contact pads. Exposed surfaces 252 on package 250 can be usedfor electrical connections (e.g., ground, power, or signal) to die 102.Various methods exist to truncate the solder spheres embedded in apackage mold, including the method illustrated in FIG. 5E, and furtherdescribed below. Additional example description for solder balltruncation and exposure on a mold top are provided in U.S. Pat. Appl.No. 60/799,657, titled “Interconnect Structure and Formation for PackageStacking of Molded Plastic Area Array Package,” filed May 12, 2006,which is incorporated by reference herein in its entirety.

In the embodiments of FIG. 2A-2E, a heat spreader is not present. Thus,thermal performance may be less than if heat spreader is present (asdescribed below). However, the improvement in thermal performance evenwithout a heat spreader may be significant in a particular applicationdue to a reduced junction-to-case thermal resistance resulting from thedisplacement of mold compound 112 by thermal interconnect members 208.

For example, in an embodiment where thermal interconnect members 208 aresolder balls, a junction-to-case thermal resistance is reduced becausethe thermal conductivity of typical (lead-free and tin/lead) IC packagesolder balls is around 50˜60 W/m*° C., which is many times higher than atypical mold compound 112, which may have a thermal conductivity ofapproximately 0.8 W/m*° C., for example. Furthermore, the solder ballsforming thermal interconnect members 208 attached to IC die 102 extendthe heat conduction area from the surface of die 102 to a top surface ofmold compound 112. The thermal performance improvement is particularlysignificant for packages with a small size of die 102, when the solderballs displace a relatively large area of mold compound 112 on the topsurface of die 102, providing a conductive path for heat dissipationthrough the top surface of package 250. Furthermore, when an externalheat sink device, such as a heat sink or a metal plate, is attached tothe top of a package such as packages 200 and 250, the thermalperformance of the package may improve. Examples of such embodiments aredescribed in detail below.

Example Embodiments of Packages with Attached Heat Spreaders

In embodiments, thermal interconnects facilitate on-chip power/heatdissipation from pre-selected locations on a semiconductor die. In anexemplary embodiment, at least one thermal interconnect is attached toan IC die and coupled to at least one heat spreader embedded or attachedto the IC package. In an example embodiment, the heat spreader isencapsulated in a mold compound. The heat spreader may be exposed on atop surface of the package for heat dissipation to the ambientenvironment, including for attachment of a heat sink. The heat spreadercan alternatively be entirely encapsulated within the mold compound of amolded IC package.

In embodiments, the heat spreader may have any of a variety of shapesand may include holes, slots, or other surface features for moldlocking, heat dissipation, stress reduction, and/or improvedreliability. The heat spreader may be made of metal such as copper,copper alloys, other materials typically used in leadframe packages(C151, C194, EFTEC-64T, C7025, etc.), aluminum, other metals orcombinations of metals/alloy, and/or thermally conductive nonmetallicmaterials. The heat spreader may be a flexible tape substrate such as apolyimide tape substrate with one or more metal foil layers laminated onpolyimide film. The heat spreader may be made of a thermally conductivebut electrically non-conductive material, such as a thermally conductiveceramic, or it may also be electrically conductive.

In an embodiment, a distance between a bottom surface of an integratedheat spreader and a top surface of the die is less than a “loop-height”of the wire bond (i.e., a distance from the apex of the wire loop to thesurface of IC die). In such an embodiment, a size of the heat spreadermay be confined by a space between the wire bond pads on the oppositesides of the top surface of the IC die.

In another embodiment, the distance between the bottom of the heatspreader and the top of die is greater than the loop-height of wirebond. In this case, the size of the heat spreader is not limited by thedistance between the bond pads on the opposite sides of the surface ofthe die. The size of the heat spreader may be greater than the size ofthe die, even if all four edges of surface of the die have wire bondinterconnections. A larger heat spreader may deliver increased hotspotcooling due to a larger area for heat dissipation. To facilitate thermalconnection, and reduce the gap between the IC die and the integratedheat spreader, a pedestal may be used that has an area less than an areaof the die, and that extends towards the top surface of the IC die.

Alternatively, thermal interconnects may be attached to the bottom ofthe heat spreader that can be thermally coupled with a correspondingthermal interconnect attached to the IC die.

In an embodiment, an integrated heat spreader is completely encapsulatedby mold compound. In another embodiment, it is partially exposed throughthe mold top, such as in manner similar to drop-in heat spreader 104shown in FIG. 1A.

In an embodiment where the thermal interconnects are electricallyconductive, one or more thermal interconnects may be attached to theground or power net of the IC die to provide an alternative route forcurrent or on-chip power delivery from the heat spreader. Examples ofsuch an arrangement are described in U.S. patent application Ser. No.10/952,172, titled “Die Down Ball Grid Array Packages And Method ForMaking Same,” filed Sep. 29, 2004, which is incorporated herein byreference in its entirety. This may be effective in reducing the lengthsof on-chip power supply current paths, thus reducing IR voltage dropswithin the IC die.

In an embodiment, the size of the heat spreader is less than a size ofthe package mold body, as illustrated in FIGS. 3A-3C. Alternatively, thesize of the heat spreader size can also be substantially the same sizeas the package mold body, or larger than the size of package mold body.Examples of this are described in U.S. patent application Ser. No.10/870,927, titled “Apparatus and Method for Thermal and ElectromagneticInterference (EMI) Shielding Enhancement in Die-Up Array Packages,”filed Jun. 21, 2004, which is incorporated by reference herein in itsentirety.

In the following paragraphs, several exemplary embodiments of theinvention are shown in various IC packages. The figures and descriptionsare not intended to limit the invention, but merely illustrate theprinciples of the operation by example. Many of the examples describedbelow include a heat spreader. However, as shown in FIGS. 2A-2F forexample, some embodiments of the invention do not have integrated heatspreaders.

Example BGA Embodiments with Integrated Heat Spreader

FIGS. 3A-3E illustrate exemplary embodiments of molded plastic finepitch ball grid array (BGA) packages having a heat spreader 302 which isat least partially covered by mold compound 112. In the embodiments ofFIGS. 3A-3E, the configuration of heat spreader 302 is varied frompackage to package.

For example, FIG. 3A illustrates a package 300 having a planar heatspreader 302 integrated with package 300 in a partially embedded manner,having a planar top surface 304 of heat spreader 302 exposed (notcovered by mold compound 112). In package 300, IC die 102 iselectrically interconnected to substrate 110 by one or more wire bonds114. One or more thermal interconnect members 208 are attached to thetop surface of die 102. Mold compound 112 encapsulates die 102, wirebonds 114, a top surface of substrate 110, and thermal interconnectmembers 208. In an embodiment, mold compound 112 can be formed onsubstrate 110 using a mold process, a saw singulation technique, orother forming technique. A planar bottom surface 306 of heat spreader302 is coupled to a top portion of each of thermal interconnect members208. In FIG. 3A, heat spreader 302 is partially encapsulated by moldcompound 112. Bottom surface 306 and the perimeter edges of heatspreader 302 are in contact with mold compound 112, while the topsurface 304 of heat spreader 302 is not covered by mold compound. Topsurface 304 of heat spreader 302 is co-planar with a top surface of moldcompound 112.

In embodiments, heat spreader 302 may be partially or completelyencapsulated by mold compound 112. Furthermore, although shown as planarin FIG. 3A, in other embodiments, heat spreader 302 may have othershapes, including regular or irregular shape and planar or non-planar.

FIG. 3B illustrates a package 350 similar to package 300, but having anon-planar heat spreader 302 integrated with package 300 in a partiallyembedded manner. In FIG. 3B, heat spreader 302 has cap-like shape, witha cavity side of heat spreader 302 facing towards die 102. Bottomsurface 306 of heat spreader 302 is coupled to a top portion of each ofthermal interconnect members 208. A planar portion 308 of top surface304 of heat spreader 302 is not covered by mold compound 112, while theremainder of heat spreader 302 is covered by mold compound 112. Forexample, a perimeter angled wall portion 310 of heat spreader 302 thatangles outward as it extends from the remaining planar portion of heatspreader 302 is covered by mold compound 112.

FIG. 3C illustrates a package 360 having a planar heat spreader 302(similar to FIG. 3A) integrated with package 360 in a non-embeddedconfiguration. Bottom surface 306 of heat spreader 302 is coupled to atop portion of each of thermal interconnect members 208. Heat spreader302 is attached to a planar top surface of mold compound 112. Thus,bottom surface 306 of heat spreader 302 is in contact with mold compound112, while the remainder of heat spreader 302 is not in contact withmold compound 112. Thus, in the embodiment of FIG. 3C, heat spreader 302can be attached to package 360 after mold compound 112 is applied.

FIG. 3D illustrates a package 370 similar to package 360, but having anon-planar heat spreader 302. Heat spreader 302 has a planar centralportion 312 connected to a surrounding plurality of leads 314 that areconfigured to couple heat spreader 302 to a circuit board (not shown inFIG. 3D) when package 370 is mounted thereto. Bottom surface 306 ofcentral portion 312 attaches thermal interconnect members 208. Leads 314of heat spreader 302 each bend down from central portion 312 at ashoulder toward the circuit board. An end of each lead 314 may have afoot 372 that bends outward from heat spreader 302, and is configured tomount to a circuit board, such as for direct thermal and/or electricalcoupling to the circuit board.

FIG. 3E illustrates a package 380, where thermal interconnect members208 are truncated solder balls having exposed surfaces 252, similar tothe configuration of FIG. 2F. Furthermore, heat spreader 302 has pads382 located at locations corresponding to surfaces 252 of thermalinterconnect members 208. Pads 382 are pre-deposited with a material 386prior to attachment to surfaces 252. Pre-deposited pads 382 may beplated with a thermally conductive material 386, such as a solder orepoxy that mechanically attaches heat spreader 302 to thermalinterconnect members 208. In an embodiment, plating material 386 is alsoelectrically conductive. Heat spreader 302 is coupled to the thermalinterconnect members 208 during a reflow, curing, or other attachmentprocess. Furthermore, in an embodiment, an air gap 384 may optionallyexist under heat spreader 302, between bottom surface 306 of heatspreader 302 and a top surface of mold compound 112, after manufactureis complete. Plating material 386 supports heat spreader 302 above moldcompound 112 at a distance to provide air gap 384.

Example PBGA Embodiments with Integrated Heat Spreader

FIGS. 4A-4B illustrate exemplary embodiments of molded plastic ball gridarray (PBGA) packages having at least one thermal interconnect member208 coupled to an integrated heat spreader 302.

FIG. 4A shows a package 400, with a partially embedded heat spreader302, according to an example embodiment of the present invention. InFIG. 4A, IC die 102 is electrically interconnected to substrate 110 bywire bonds 114. One or more thermal interconnect members 208 are coupledbetween die 102 and heat spreader 302. Furthermore, thermal interconnectmembers 208 are shown having a truncated top portion, similar to asdescribed above with respect to FIG. 2F. Bottom surface 306 of heatspreader 302 attaches to top surfaces 252 of thermal interconnectmembers 208. Mold compound 112 is formed by a molding process, andencapsulates much of package 400, including die 102, wire bond 114, aportion of the top surface of substrate 110, and all of heat spreader302 except for a planar top portion 402 of heat spreader 302.

In FIG. 4A, heat spreader 302 is cap-shaped, having a cavity 474 facingtowards die 102, and enclosing thermal interconnect members 208, die102, and wire bonds 114 on the top surface of substrate 110. The capshape of heat spreader 302 has an top planar portion, outward slantingside walls that extend downward from the top planar portion and thatsurround cavity 474, and a perimeter rim portion 404 around a bottomedge of the side walls. A bottom surface of perimeter rim portion 404 ofheat spreader 302 is attached to the top surface of substrate 110 by anadhesive material 406, such as an epoxy, adhesive, solder, or otheradhesive.

Heat spreader 302 may be any regular or irregular shape, and planar ornon-planar. For example, FIG. 4B shows a package 450 similar to package400 of FIG. 4A, except that heat spreader 302 is planar in shape. Topsurface 304 of heat spreader 302 is not covered by mold compound 112.The outer edges of heat spreader 302 are covered by mold compound 112.Bottom surface 306 of heat spreader 302 is embedded in mold compound112, and attaches to top surfaces 252 of thermal interconnect members208.

Example Leadframe Embodiments with Integrated Heat Spreader

Embodiments of the invention can be implemented in many IC packages. Forexample, FIGS. 5A-5C illustrate example embodiments having at least onethermal interconnect member 208 and a heat spreader 502 integrated witha leadframe package. For example, FIG. 5A illustrates a package 500 inwhich die 102 is attached to a die attach pad 504 of a leadframe 516.Leadframe 516 includes a plurality of leads 518 and die attach pad 504.Die 102 is electrically interconnected with die attach pad 504 and/orleads 518 by one or more wire bonds 514. Furthermore, leads 518 may beelectrically interconnected with die attach pad 504 with one or morewire bonds 514. Heat spreader 502 is cap-shaped, having a cavity 520facing towards die 102. Die 102 and a bottom surface 522 in cavity 520of heat spreader 502 are connected by one or more thermal interconnectmembers 208, which may or may not be truncated.

Package 500 is encapsulated by mold compound 512, which fills a gapbetween heat spreader 502 and die 102, including cavity 520. A bottomsurface of a perimeter rim portion 524 of heat spreader 502 is mountedto lead frame 516. As shown in FIG. 5A, the bottom surface of perimeterrim portion 524 and lead frame 516 may be configured to interlock forimproved mechanical coupling.

FIG. 5B illustrates a package 550 similar to package 500 of FIG. 5A,except that heat spreader 502 is planar, and thus is not mounted to leadframe 516.

FIG. 5C illustrates a package 560 similar to package 550 of FIG. 5B,except that heat spreader 502 is completely embedded in mold compound112.

Note that although die-up configurations (i.e., circuit side of die 102is facing away from the circuit board when mounted thereto) are shown inFIG. 5A-5C, these are shown for the purpose of illustration. Embodimentsof the present invention are also applicable to die-down leadframepackages.

In another embodiment, one or more thermal interconnect members 208 maybe used in a leadframe package without an integrated heat spreader, in asimilar manner as shown in FIG. 2A-2F for BGA packages.

Example QFN Package Embodiments with Integrated Heat Spreader

FIGS. 6A and 6B illustrate example embodiments of no-lead quad flatpackages (QFP), also known as micro leadframe packages (MLP) or microlead frame (MLF) IC packages, each having at least one thermalinterconnect member 208 and a heat spreader 602 integrated therein. Forexample, FIG. 6A illustrates a package 600 in which die 102 is attachedto a die attach pad 604. Die 102 is electrically interconnected with dieattach pad 604 and/or leads 616 by one or more wire bonds 614. Heatspreader 602 is cap-shaped, having a cavity 620 facing towards die 102.Die 102 and a bottom surface 622 in cavity 620 of heat spreader 602 areconnected by one or more thermal interconnect members 208, which may ormay not be truncated.

Package 600 is encapsulated by mold compound 612, which fills a gapbetween heat spreader 602 and die 102, including cavity 620. A bottomsurface of a perimeter rim portion 624 of heat spreader 602 is mountedto leads 616. As shown in FIG. 6A, the bottom surface of perimeter rimportion 624 and leads 616 may be configured to interlock for improvedmechanical coupling.

FIG. 6B illustrates a package 650 similar to package 600 of FIG. 6A,except that heat spreader 602 is planar, and thus is not mounted toleads 616.

Example Embodiment of a Manufacturing Process for IC Packages:Encapsulate Before Attaching Optional Heat Spreader

FIG. 7A shows a flowchart 700 providing an example process formanufacturing embodiments of the invention. Flowchart 700 is describedwith reference to FIGS. 7B-D, which show a BGA package at various stagesof manufacture. Flowchart 700 may be applied in a modified ornon-modified manner to manufacture other package types, as would beunderstood by persons skilled in the relevant art(s) from the teachingsherein. In flowchart 700, an optional step of attaching a heat spreader(step 710) may be performed depending on whether a heat spreader isdesired to be present.

Flowchart 700 begins with step 701. In step 701, a die is mounted to asubstrate. For example, the die is die 102 shown in FIGS. 2A-2C, whichis attached to substrate 110 using die attach material 106. Die attachmaterial 106 may be any type of suitable adhesive material, such as anepoxy and/or film adhesive, or other type of adhesive material orattachment mechanism.

In step 702, thermal interconnects are mounted on a top surface of thedie. For example, one or more thermal interconnect members 208 aremounted on contact pads 202 on die 102, as shown in FIGS. 2A-2C. FIG. 7Billustrates an example partially assembled package 750 after steps 701and 702. In an embodiment, a conventional ball mount process used formounting solder balls to the bottom of BGA packages may be used to mounta solder ball to die 102, when thermal interconnect members 208 aresolder balls.

In step 704, wire bonds are coupled between the die and substrate. Forexample, die 102 may be electrically connected to substrate 110 througha wire bonding process that attaches wire bonds 114. FIG. 7C illustratesan example partially assembled package 760 after steps 701-704.

In step 706, the package is encapsulated in mold compound. For example,the mold compound is mold compound 112. As shown in FIGS. 2A-2C, moldcompound 112 covers die 102, wire bond 114, at least one thermalinterconnect member 208, and all or part of substrate 110. FIG. 7Dillustrates an example a partially assembled package 770 after steps701-706.

In an optional step 708, a portion or all of a top layer of the moldcompound is removed. For example, in an embodiment, a layer of moldcompound 112 is removed such that one or more thermal interconnectmembers 208 are truncated (i.e., a top portion of thermal interconnectmember 208 is removed along with a portion of the top layer, or theentire top layer of mold compound 112).

FIG. 7A shows step 708 as optionally including one of steps 708 a and708 b. In optional step 708 a, an entire top layer of the mold compoundis removed, such as shown in FIG. 2F. FIG. 7E illustrates an exampleimplementation of step 708 a, where a grinding tool 702 is used to grindaway an entire top layer of molding compound 112, thereby grinding awaya portion of thermal interconnect members 208 and exposing surface 252of thermal interconnect members 208.

In optional step 708 b, a cavity is formed in the mold compound. FIG. 7Fillustrates an example implementation of step 708 b. As shown in FIG.7F, a routing tool 704 is used to route away a central portion of a toplayer of mold compound 112 to form a cavity 706 in the top layer of moldcompound 112. In the process of forming cavity 706, routing tool 704routes away a portion of thermal interconnect members 208 that are undercavity 706, to expose surface 252 of the centrally located thermalinterconnect members 208.

In embodiments, other methods of material removal than those describedabove may be used in steps 708, 708 a, and 708 b to remove mold topmaterial and expose and/or truncate one or more thermal interconnects.Other surface machining methods such as etching or laser machining mayused to remove mold material and expose thermal/electrical interconnectelements.

As described above, step 708 (and sub-steps 708 a and 708 b) isoptional. In an alternative embodiment, step 708 is not performed, and alayer and/or cavity of mold compound is not removed.

In optional step 710, a heat spreader is attached to the package. Forexample, the heat spreader is heat spreader 302, 502, 602, or 702,described above. In an embodiment of a package not having a heatspreader, optional step 710 is not performed. When step 710 isperformed, the heat spreader is coupled to the one or more exposedthermal interconnects, which may or may not be truncated.

Note that the steps of flowchart 700 may be performed in orders otherthan shown in FIG. 7A. For example, step 704 may be performed beforethermal interconnects are attached to the die surface in step 702.

FIG. 8A illustrates a flowchart 800 showing a process for attaching aheat spreader to an IC package. Flowchart 800 is described withreference to FIGS. 8B-C, which show a BGA package at various stages ofmanufacture. Flowchart 800 may be applied in a modified or non-modifiedmanner to manufacture other package types, as would be understood bypersons skilled in the relevant art(s) from the teachings herein

Flowchart 800 begins in step 802. In step 802, a heat spreader havingone or more pre-plated pads is received. For example, the heat spreaderis heat spreader 302, as shown in FIG. 8B. FIG. 8B shows a partiallyassembled package 850 and heat spreader 302. Heat spreader 302 has pads382 that are plated with plating material 386. Plating material 386 maybe a thermally conductive substance, for example, solder or epoxy.

In step 804, the heat spreader is placed on the package. For example, asshown in FIG. 8C, heat spreader 302 is placed on partially assembledpackage 860, such that plating material 386 is in contact with surface252 of thermal interconnects 252.

In step 806, the heat spreader is caused to become attached to thepackage. For example, to attach the heat spreader and package, a reflowor curing process may be conducted. The reflow or curing process causesheat spreader 302 to become attached to partially assembled package 860,to form package 870, as illustrated in FIG. 8C. A reflow process may beused for a solder plating embodiment for plating material 386, or acuring process may be used for an epoxy material embodiment of platingmaterial 386. After assembly, the completed package may have an air gap384 between heat spreader 302 and mold compound 112.

Example Embodiment of Manufacturing Processes for IC Packages:Encapsulate after Attaching Heat Spreader

FIG. 9A shows a flowchart 900 providing an example process formanufacturing embodiments of the invention. Flowchart 900 is describedwith reference to FIGS. 9B-D, which show a BGA package at various stagesof manufacture. Flowchart 900 may be applied in a modified ornon-modified manner to manufacture other package types, as would beunderstood by persons skilled in the relevant art(s) from the teachingsherein.

Flowchart 900 begins with step 902. In step 902, a die is mounted to asubstrate. For example, the die is die 102 of FIG. 3A, which is attachedto substrate 110.

In step 904, wire bonds are coupled between the die and the substrate.For example, as shown in FIG. 3A, die 102 is electrically connected tosubstrate 110 through a wire bonding process that applies wire bonds114.

In step 906, thermal interconnects are mounted to a top surface of thedie. For example, one or more thermal interconnect members 208 may bemounted to contact pads 202 on the top surface of die 102. FIG. 9Billustrates an example partially assembled package 920 after steps 902,904, and 906. In an embodiment, a conventional ball mount process usedfor mounting solder balls to the bottom of BGA packages is used to mounta thermal interconnect members 208 to die 102.

In step 908, the heat spreader is attached to the thermal interconnects.For example, as shown in FIG. 3A, heat spreader 302 is attached tothermal interconnect members 208. In a further embodiment, heat spreader302 may have pre-plated pads, such as shown in FIG. 3E. FIG. 9Cillustrates an example partially assembled package 930 after steps902-908.

In step 910, the package is encapsulated in mold compound. For example,as shown in FIG. 3A, mold compound 112 covers die 102, wire bond 114, atleast one thermal interconnect member 208, and all or part of substrate110. FIG. 9D illustrates an example partially assembled package 940after steps 902-910.

Note that the steps of flowchart 900 may be performed in orders otherthan shown in FIG. 9A. For example, step 906 may be performed beforestep 904.

In a further embodiment, thermal interconnects may be attached to theheat spreader before being attached to the die. FIG. 9E shows aflowchart 950 providing an example process for manufacturing embodimentsof the invention. Flowchart 950 is described with reference to FIGS.9F-H, which show a BGA package at various stages of manufacture.Flowchart 950 may be applied in a modified or non-modified manner tomanufacture other package types, as would be understood by personsskilled in the relevant art(s) from the teachings herein.

Flowchart 950 begins with step 952. In step 952, a die is mounted to asubstrate. For example, the die is die 102 of FIG. 3A, which is attachedto substrate 110.

In step 954, wire bonds are coupled between the die and the substrate.For example, as shown in FIG. 3A, die 102 is electrically connected tosubstrate 110 through a wire bonding process that applies wire bonds114.

In step 956, thermal interconnects are mounted to a bottom surface ofthe heat spreader. For example, one or more thermal interconnect members208 may be mounted to bottom surface 306 of heat spreader 302, as shownin FIG. 9F. In an embodiment, a conventional ball mount process used formounting solder balls to the bottom of BGA packages is used to mountthermal interconnect members 208 to heat spreader 302. In a furtherembodiment, heat spreader 302 has pre-plated pads (not shown in FIG.9F).

In step 958, the thermal interconnects are attached to the top surfaceof the die. For example, thermal interconnect members 208 are attachedto die 102. FIG. 9G illustrates an example partially assembled package980 after step 958.

In step 960, the package is encapsulated in mold compound. For example,mold compound 112 is used to cover die 102, wire bonds 114, thermalinterconnect members 208, and all or part of substrate 110. FIG. 9Hillustrates an example partially assembled package 990 after completionof steps 902-910.

Example Embodiments of Substrate Coupled Heat Spreader

In embodiments, thermal interconnect members may be used to couple aheat spreader to a substrate in an integrated circuit package. Forexample, FIGS. 10A-10C illustrate cross-sectional views of example BGApackages having a heat spreader thermally coupled to the packagesubstrate, according to exemplary embodiments of the invention. Theembodiments of FIGS. 10A-10C are provided for illustrative purposes. Inalternative embodiments, thermal interconnect members may be used inother types of IC packages to couple heat spreaders to substrates.Furthermore, when the thermal interconnect members are solder balls,they may be truncated or non-truncated. Other materials such as copper,gold, other metals and/or metal alloys can be used for thermalinterconnect members, including the materials described elsewhere hereinor otherwise known.

The packages of FIGS. 10A-10C are generally similar to package 300 ofFIG. 3A, with some differences described as follows. FIG. 10A shows apackage 1000 having a plurality of thermal interconnect members 208 thatcouple bottom surface 306 of heat spreader 302 to a top surface 1002 ofsubstrate 110. In an embodiment, thermal interconnect members 208provided a thermally conductive path between substrate 110 and heatspreader 302, such that heat generated by die 102 that passes intosubstrate 110 can be transferred to heat spreader 302.

Thermal interconnect member 208 may be coupled to top surface 1002 ofsubstrate 110 at a non-electrically conductive location of substrate 110and/or an electrically conductive location of substrate 110. Forexample, a bottom surface of thermal interconnect member 208 may beattached to a surface of a solder resist layer or dielectric layer ofsubstrate 110, which are typically non-electrically conductive, and havea relatively low degree of thermal conductivity. In another example, thebottom surface of thermal interconnect member 208 may be attached to anelectrically conductive feature 1004 of substrate 110, such as a trace,bond finger, contact pad, ground/power ring, etc., which are typicallymade of a metal (e.g., a metal foil, plating, etc) such as copper,aluminum, gold, tin, nickel, silver, another metal, or combination ofmetals/alloy.

In an embodiment where thermal interconnect member 208 coupleselectrically conductive feature 1004 of substrate 110 to heat spreader302, thermal interconnect member 208 may provide an electricallyconductive path to heat spreader 302 when thermal interconnect member208 is electrically conductive.

As shown in FIG. 10A, heat spreader 302 has an area that is smaller thanan area of a top surface of mold compound 112, such that a peripheralarea of the top surface of mold compound 112 is not covered by heatspreader 302. FIG. 10B shows a package 1010 similar to package 1000 ofFIG. 10A, except that heat spreader 302 has an area substantially thesame as an area of the top surface of mold compound 112.

Any number of thermal interconnect members 208 may be present inembodiments to couple heat spreader 302 to substrate 110, including anarray of thermal interconnect members 208. For example, in FIGS. 10A and10B, a pair of rings of thermal interconnect members 208 encircle die102 on top surface 1002 of substrate 110. Any number of such rings ofthermal interconnect members 208 may be present, when desired. FIG. 10Cshows a package 1020 similar to package 1010 of FIG. 10B, except that asingle ring of thermal interconnect members 208 encircle die 102 on topsurface 1002 of substrate 110.

In embodiments, flowcharts 700, 900, and 950, can be modified to includea step of forming/attaching thermal interconnects to a heat spreaderand/or to a substrate to be used to couple the heat spreader to thesubstrate.

Note that although FIGS. 10A-10C show thermal interconnect members 208coupled between substrate 110 and heat spreader 302, packages 1000,1010, 1020 may also include thermal interconnect members 208 couplingthe top surface of die 102 to heat spreader 302.

CONCLUSION

While various embodiments of the present invention have been describedabove, it should be understood that they have been presented by way ofexample only, and not limitation. It will be apparent to persons skilledin the relevant art that various changes in form and detail can be madetherein without departing from the spirit and scope of the invention.Thus, the breadth and scope of the present invention should not belimited by any of the above-described exemplary embodiments, but shouldbe defined only in accordance with the following claims and theirequivalents.

What is claimed is:
 1. A method of manufacturing an integrated circuit(IC) package, the method comprising: attaching an IC die to a substrate,the IC die having a contact pad located at a hotspot on a surface of theIC die that radiates more heat relative to a second location on thesurface of the IC die during operation of the IC die; coupling at leastone wire bond between the IC die and the substrate; coupling a thermalinterconnect member to the contact pad; and encapsulating the IC die,the at least one wire bond, and at least a portion of the thermalinterconnect member in a mold compound.
 2. The method of claim 1,further comprising exposing the thermal interconnect member.
 3. Themethod of claim 2, wherein the exposing the thermal interconnect membercomprises removing a layer of the mold compound.
 4. The method of claim2, wherein the exposing the thermal interconnect member comprisesremoving a portion of a layer of the mold compound.
 5. The method ofclaim 1, further comprising coupling a heat spreader to the thermalinterconnect member.
 6. The method of claim 5, wherein the heat spreaderhas a plated area, and wherein the coupling the heat spreader to thethermal interconnect member comprises: attaching the plated area to asurface of the thermal interconnect member.
 7. The method of claim 1,wherein the coupling the thermal interconnect member to the contact padcomprises: coupling at least one additional thermal interconnect memberto at least one additional contact pad on the surface of the IC die, theat least one additional contact pad being located on at least oneadditional hotspot on the surface of the IC die.
 8. The method of claim7, further comprising coupling a heat spreader to the thermalinterconnect member and the at least one additional thermal interconnectmember.
 9. The method of claim 1, further comprising forming a cavity ina surface of the mold compound.
 10. The method of claim 9, furthercomprising mounting a heat spreader in the cavity of the surface of themold compound.
 11. The method of claim 1, wherein the thermalinterconnect member is a solder ball, and wherein the coupling thethermal interconnect member to the contact pad comprises mounting thesolder ball to the contact pad.
 12. The method of claim 2, wherein thethermal interconnect member is a solder ball, and wherein the couplingthe thermal interconnect member to the contact pad comprises truncatingthe solder ball.
 13. The method of claim 1, further comprisingperforming a thermal analysis of the IC die to determine at least onehotspot of the IC die.
 14. A method of manufacturing an integratedcircuit (IC) package, comprising: attaching an IC die to a substrate;coupling a thermal interconnect member to the substrate; encapsulatingthe IC die and at least a portion of the thermal interconnect member ina mold compound; and coupling the thermal interconnect member to a heatspreader.
 15. The method of claim 14, wherein the coupling the thermalinterconnect member to the substrate comprises: attaching a secondthermal interconnect member to a contact pad located on a surface of theIC die at a hotspot that radiates more heat relative to a secondlocation on the surface of the IC die during operation of the IC die.16. The method of claim 14, wherein the thermal interconnect member is asolder ball, wherein the coupling the thermal interconnect member to thesubstrate comprises coupling the solder ball to the substrate.
 17. Themethod of claim 14, wherein: the coupling the thermal interconnectmember to the substrate comprises coupling a plurality of thermalinterconnect members to the substrate; and the coupling the thermalinterconnect member to the heat spreader comprises coupling theplurality of thermal interconnect members to the heat spreader.
 18. Anintegrated circuit (IC) package, comprising: an IC die having a surface;and a set of thermal interconnect members, wherein each thermalinterconnect member of the set of thermal interconnect members is:coupled to a respective one of a plurality of hotspots located on thesurface of the IC die; and configured to conduct heat from therespective hotspot of the plurality of hotspots to uniformly distributeheat throughout the IC die during operation.
 19. The IC package of claim18, wherein each thermal interconnect member of the set of thermalinterconnect members is further configured to cause a temperature of arespective location on the IC die to decrease towards a temperature ofanother location on the IC die during operation of the IC die.
 20. TheIC package of claim 18, further comprising: a mold compound thatencapsulates the IC die and at least a portion of each thermalinterconnect member of the set of thermal interconnect members.
 21. TheIC package of claim 20, wherein a surface of the mold compound has acavity formed therein.
 22. The IC package of claim 21, furthercomprising: a heat spreader coupled to each thermal interconnect memberof the set of thermal interconnect members, wherein the heat spreader ismounted in the cavity.
 23. The IC package of claim 20, wherein a portionof each thermal interconnect member of the set of thermal interconnectmembers is exposed at a surface of the mold compound.